The paper presents the results of an experimental characterization about the operation of the last generation normally-off SiC JFETs at the edges of their safe operating area. Short circuit and unclamped turn-off operations have been investigated by means of a nondestructive experimental set up where the device is switched in the presence of a protection circuit capable of limiting the energy dissipated on the device after the failure occurrence. The experimental results confirm the very good performances of the device in short circuit for which the failure can be associated only to the increase of the temperature over the limits imposed by the surface metallization. A different scenario appears for the unclamped tests where a second breakdown occurs after a quite long avalanche phase followed by the device failure. It is demonstrated that the duration of the avalanche phase depends on the temperature of the device under test. The damaged area after an avalanche failure is localized at the edge termination of the device and, in particular, at the corner between source and gate metallization.

Operation of SiC normally-off JFET at the edges of its safe operating area

ABBATE, Carmine;BUSATTO, Giovanni;IANNUZZO, Francesco
2011

Abstract

The paper presents the results of an experimental characterization about the operation of the last generation normally-off SiC JFETs at the edges of their safe operating area. Short circuit and unclamped turn-off operations have been investigated by means of a nondestructive experimental set up where the device is switched in the presence of a protection circuit capable of limiting the energy dissipated on the device after the failure occurrence. The experimental results confirm the very good performances of the device in short circuit for which the failure can be associated only to the increase of the temperature over the limits imposed by the surface metallization. A different scenario appears for the unclamped tests where a second breakdown occurs after a quite long avalanche phase followed by the device failure. It is demonstrated that the duration of the avalanche phase depends on the temperature of the device under test. The damaged area after an avalanche failure is localized at the edge termination of the device and, in particular, at the corner between source and gate metallization.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11580/18353
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