Recently, an all-digital overlay system has been developed in for providing useful management functionalities in optically routed networks. The main feature of the system is to overlay a low-rate stream of management data on a high-rate payload data channel so that the low-rate stream can be recovered by low-cost decoders located at various points within the network. The two key components of the overlay architecture are (i) a constant weight code used for multiplexing payload data streams, and (ii) a CDMA-based protocol used for managing interference among auxiliary data streams. In this work, we provide a general analysis under chip-asynchronous conditions, thereby extending a previous study under chip-synchronous conditions. Our analysis reveals that the bit error rate of the management data channel is limited by the presence of the payload interference. We show that significant performance improvements can be achieved by exploiting the covariance structure of the payload interference and investigate several low-complexity linear detection strategies. Analytical and numerical performance results are provided, and fundamental tradeoffs among several system parameters are identified.

Effect of chip-level asynchronism on a CDMA-based overlay system for optical network management

VENTURINO, Luca;
2010-01-01

Abstract

Recently, an all-digital overlay system has been developed in for providing useful management functionalities in optically routed networks. The main feature of the system is to overlay a low-rate stream of management data on a high-rate payload data channel so that the low-rate stream can be recovered by low-cost decoders located at various points within the network. The two key components of the overlay architecture are (i) a constant weight code used for multiplexing payload data streams, and (ii) a CDMA-based protocol used for managing interference among auxiliary data streams. In this work, we provide a general analysis under chip-asynchronous conditions, thereby extending a previous study under chip-synchronous conditions. Our analysis reveals that the bit error rate of the management data channel is limited by the presence of the payload interference. We show that significant performance improvements can be achieved by exploiting the covariance structure of the payload interference and investigate several low-complexity linear detection strategies. Analytical and numerical performance results are provided, and fundamental tradeoffs among several system parameters are identified.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11580/13786
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